FM demodulation or detection can
be directly achieved using the PLL circuit. If
the PLL center frequency is
selected or designed at the FM carrier frequency, the filtered or output voltage
of the circuit is the desired
demodulated voltage, varying in value proportional to the variation of the
signal frequency. The PLL circuit thus operates as a complete
intermediate-frequency (IF) strip, limiter, and demodulator as used in FM
receivers.
One popular PLL , The 565 contains a phase detector, amplifier,
and voltage-controlled oscillator, which are only partially connected internally.
An external resistor and capacitor, R1 and C1, are used to set
the free-running or center frequency of the VCO. Another external capacitor, C2,
is used to set the low-pass filter passband, and the VCO output must be
connected back as input to the phase detector to close the PLL loop. The 565
typically uses two power supplies, V_ and V.
The signal at pin 4
is a 136.36-kHz square wave. An input within the lock range of
181.8 kHz will result
in the output at pin 7 varying around its dc voltage level set
with input signal at fo.
the output at pin 7 as a function of
the input signal frequency. The dc voltage at pin 7 is linearly related to the
input signal
frequency within the
frequency range fL _ 181.8
kHz around the center frequency
136.36 kHz. The
output voltage is the demodulated signal that varies with frequency within the operating range specified.
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