The Junction field Effect transistor (JFET)

The Junction Field Effect Transistor (JFET)

Bipolar junction transistors have low input impedance, small high-frequency gain and are non-linear when |VCE| < 2 V. The input impedance is naturally restricted by the forwardbiased base-emitter junction. There are always problems due to the main charge carriers passing through the region where the majority carriers are of opposite polarity.

The junction field effect transistor (JFET) overcomes some of the problems of the bipolar junction transistor. JFETs come in two types: N-channel and P-channel.

.

The designation refers to the polarity of the majority charge carriers in the bar of semiconductor that connects the drain terminal D to the source terminal S. Since the channel is formed from a single-polarity (unipolar) material, its resistance is a function only of the geometry of the conducting volume and the conductivity of the material. The JFET operates with all PN junctions reverse-biased so as to obtain a high input impedance into the gate.

1. Principles of Operation

An N-channel JFET with DC bias voltage applied. Just as for a simple

diode, the depletion region grows as the reverse bias across the PN junction is increased, thereby constricting the cross section of the conducting N-channel material and increasing the resistance of the channel. The major current ID in the channel is caused by the applied voltage between the drain and source, VDS, and is controlled by the applied voltage between the gate and source, VGS.

N−Channel P−Channel

Basic geometry and circuit symbols of JFETS.

The JFET has two distinct modes of operation: the variable-resistance mode, and the

pinch-off mode. In the variable-resistance mode the JFET behaves like a resistor whose value is controlled by VGS. In the pinch-off mode, the channel has been heavily constricted with most of the drain-source voltage drop occuring along the narrow and therefore high-resistance part of the channel near the depletion regions.

The characteristic curves of a typical JFET . At small values of VDS (in the range of a few tenths of a volt), the curves of constant VGS show a linear relationship between VDS and ID. This is the variable-resistance region of the graph. As VDS increases, each of the curves of constant VGS enters a region of nearly constant ID

.

This is the pinch-off region, where the JFET can be used as a linear voltage and current

amplifier. At VGS = 0 the current through the JFET reaches a maximum known as IDSS,

the current from Drain to Source with the gate Shorted to the source. If VGS goes positive for this N-channel JFET, the PN junction becomes conducting and the JFET becomes just a forward-biased diode.